Learn with SHAKTI
SHAKTI is an open-source initiative by the Reconfigurable Intelligent Systems Engineering (RISE) group at IIT-Madras. The SHAKTI project is building a family of 6 processors, based on the RISC-V ISA. The project has currently developed a Embedded class (called E-Class) and Controller class (called C-Class) of processor based on the RISC-V ISA. RISC-V (pronounced “risk-five”) is a free and open Instruction Set Architecture (ISA) enabling a new era of processor innovation through open standard collaboration.
RISC-V ISA Overview
RISC-V was originally designed to support computer architecture research and education. But now it has become a standard free and open architecture for industry implementations. RISC-V ISA is defined as a base integer ISA, which must be present in any implementation, plus optional extensions to the base ISA. Each base integer instruction set is characterized by the width of the integer registers and the corresponding size of the address space and by the number of integer registers. RISC-V is little-endian and comes in 32 and 64 bit flavours. For both, int is 32 bits. Pointers and long are of native register size. Signed values are always sign extended in a larger register. Unsigned 8/16-bit values are zero extended. Unsigned 32-bit values are sign-extended. RISC-V has been designed to support extensive customization and specialization. RISC-V spec has two volumes, User level Spec and Privelege level Spec.