Learn with SHAKTI

Introduction

SHAKTI is an open-source initiative by the Reconfigurable Intelligent Systems Engineering (RISE) group at IIT-Madras. The SHAKTI project is building a family of 6 processors, based on the RISC-V (pronounced “risk-five”) Instruction Set Architecture. The project has currently developed a Embedded class (called E-Class) and Controller class (called C-Class) of processor based on the RISC-V ISA. SHAKTI is currently supported on Arty-7 35t and Arty-7 100T boards. "Learn with Shakti" is a medium to learn RISC-V assembly programming and use SHAKTI development boards


RISC-V ISA Overview


RISC-V is a open standard Instruction Set architecture based on the Reduced Instruction Set Computing (RISC) principles. It was originally designed to support computer architecture research and education. But now it is adopted by many industries and academia. RISC-V is little-endian, and comes in 32 and 64 bit flavors. RISC-V has a wide hardware and software ecosytem. GCC, Linux, Qemu, Gem-5, GDB, OpenOCD, Eclipse are some of the wellknown software's that have architectural support for RISC-V. In the "Learn with Shakti", we start with writing basic assembly program and compiling it in RISC-V GCC. We learn to use RISC-V GDB and simulate RISC-V assembly programs in Spike simulator. Finally we end up with is running programs on Shakti development boards. The RISC-V specification consists of two volumes, User level Spec and Privilege level Spec. The RISC-V specification has enough instructions to support existing operating systems and softwares. RISC-V has been designed to support extensive customization and specialization. Furthermore, SHAKTI class of processors are RISC-V compliant.