Shakti Processors

SHAKTI has envisioned a family of processors as part of its road-map, catering to different segments of the market.


This is our embedded class processor, built around a 3-stage in-order core. It is aimed at low-power and low compute applications and is capable of running basic RTOSs like FreeRTOS, Zephyr and eChronos. Market segments include: smart-cards, IoT sensors, motor controls and robotic platforms

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The C Class is a controller class of processors, aimed at mid-range application workloads. The core is a highly optimized, 5-stage in-order design with MMU support and capability to run operating systems Linux and Sel4. These processors are targeted at compute/control applications in the 0.5-1.5 Ghz range.The C-class supports the full RISC-V ISA. The C Class is also the basis for our Tagged-ISA and Fault tolerant cores.

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Equipped with performance oriented features like out-of-order execution, multi-threading, aggressive branch prediction, non-blocking caches and deep pipeline stages. The I-Class processors are targeted at the compute , mobile, storage e and networking segments. Target operating range - 1.5-2.5 Ghz.

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Multicore Processors


This is a mobile class processor with a maximum of 8 cores, the cores being a combination of C and I class cores.Tile-Link is used as the cache-coherent interconnect used along with transaction adapters/bridges to AXI4/AHB to connect to fast and/or slow peripherals. The TileLink topology is customizable to allow optimizations for various power/performance targets. In typical configurations, it is expected that a core complex of 2 or 4 cores will share an L2 cache. L3 caches are optional and are typically expected to be used in desktop type applications.


The S-Class is aimed at Workstation and Enterprise server workloads. The base core is an enhanced version of the I-class, with quad-core and multi-threading support. A tile-link based cache coherent mesh fabric is the interconnect of choice. Cores are expected to use dedicated L2 caches and segmented L3 caches. A maximum core count of 32 will be supported. External interconnect is expected to be Gen-Z and we are considering supporting multi-socket cache coherency based on a MOESIF style protocol running on top of Gen-Z.


SoC configuration aimed at highly parallel enterprise, HPC and analytics workloads. The cores can be a combination of C or I class, single thread performance driving the core choice. Optional L4 caches and an optimized memory hierarchy is key to achieving a high memory bandwidth The architecture thrust is on accelerators, VPU and AI/ML and an mesh SoC fabric optimized for up to 128 cores with multiple accelerators per core. Close integration with an external Gen-Z fabric is a key part of the design, as is support for storage class memory. This aspect of the design is crucial since I/O and memory bandwidth is often the bottleneck for these classes of processors.

Experimental Processors


A variant of the C-Class that explores tag based ISAs for object level security. We plan to support coarse and fine grain tags. Coarse grain tags will be used to realize micro-VM like functionality to mitigate software attacks like buffer-overflow.

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F-Class processors are fault tolerant versions of the base-processors.Features include redundant compute blocks (like DMR and TMR), temporal redundancy modules to detect permanent faults, lock-step core configurations, fault localization circuits,ECC for critical memory blocks and redundant bus fabrics. These are also a key component of our ASIL-D solutions and autonomous vehicle compute blocks.

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