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CS2610: Assembly Language Lab
Assignment 4 (Paging and PMP)
Madhu designed a software, which loads at memory address 0x10010000. The software is split into two modules, the Machine mode module that can be executed only in Machine Mode and the Supervisor mode module that can be executed in both Machine and Supervisor mode. The machine mode code is inaccessible from Supervisor mode. Madhu also set up a Memory Management Unit with pages of size 10KB or more. The software was made ready for x86 processor based boards. Due to Covid19 lockdown, the x86 processor based boards were not shipped. So Madhu decided to purchase indigenous boards. He choose to buy Shakti C class procesor based boards. Before that, he wanted to verify the software through spike simulation. Please write an assembly program for the above software design and verify it in spike.
4.2 Paging and PMP
Prof. Batterywala asked his students to design a Memory Management Unit with support for 3 level page table. He also put in the following restrictions: a. The Machine mode code excluding the trap handler part is read, write and execute protected. b. The supervisor code consists of two pages. One page has a dummy process (infinite loop) running and the second page has the supervisor trap handler. This trap handler should demonstrate the page miss handling, for the first page access.