Family of processors, catering to different segments of the market.

Base Class Of Processors


An Embedded class processor, built around a 3-stage in-order core. It is aimed at low-power and low compute applications. It is capable of running basic RTOSs like FreeRTOS, Zephyr and eChronos. Market segments include: Smart-cards, IoT devices, motor controls and robotic platforms.

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A controller class of processor, aimed at mid-range application workloads. The core is highly optimized, 5-stage in-order design with MMU support and capability to run operating systems Linux and Sel4. C-class targets compute/control applications in the 0.5-1.5 Ghz range.

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Equipped with performance oriented features like out-of-order execution, multi-threading, aggressive branch prediction, non-blocking caches and deep pipeline stages. The I-Class targets the compute, mobile, storage and networking segments. Target operating range is 1.5-2.5 Ghz.

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Multicore Processors


A mobile class processor with a maximum of 8 cores, the cores being a combination of C and I class cores.Tile-Link is used as the cache-coherent interconnect used along with transaction adapters/bridges to AXI4/AHB to connect to fast and/or slow peripherals. The TileLink topology is customizable to allow optimizations for various power/performance targets. In typical configurations, it is expected that a core complex of 2 or 4 cores will share an L2 cache. L3 caches are optional and are typically expected to be used in desktop type applications.


Aimed at Workstation and Enterprise server workloads. The base core is an enhanced version of the I-class, with quad-core and multi-threading support. A tile-link based cache coherent mesh fabric is the interconnect of choice. Cores are expected to use dedicated L2 caches and segmented L3 caches. A maximum core count of 32 will be supported. External interconnect is expected to be Gen-Z and we are considering supporting multi-socket cache coherency based on a MOESIF style protocol running on top of Gen-Z.


A SoC configuration aimed at highly parallel enterprise, HPC and analytics workloads. The cores can be a combination of C or I class, single thread performance driving the core choice. Optional L4 caches and an optimized memory hierarchy to achieve a high memory bandwidth. The architecture thrust is on accelerators, VPU and AI/ML and an mesh SoC fabric optimized for up to 128 cores with multiple accelerators per core. Close integration with an external Gen-Z fabric is a key part of the design, as is support for storage class memory.

Experimental Processors


A variant of the C-Class that explores tag based ISAs for object level security. Designed to support coarse and fine grain tags. Coarse grain tags will be used to realize micro virtual machine like functionality to mitigate software attacks like buffer-overflow.

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Fault tolerant version of the base class processor. Features include redundant compute blocks (like DMR and TMR), temporal redundancy modules to detect permanent faults, lock-step core configurations, fault localization circuits, ECC for critical memory blocks and redundant bus fabrics.

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