Cryptography plays a vital role in securing e-business and e-commerce transactions. However, in spite of their mathematical robustness when these algorithms are implemented they may leak sensitive information via unintended side channels. The focus of this workshop is to delve into these side channels which exist when these ciphers are executed on computers which are built utilizing modern day computer architectures. It has been actively researched that with the advancement of such architectures, which has primarily been driven by performance, efficient attacks are possible leading to devastating attacks. The workshop focusses on cache attacks and its influence on timing side channels. Cache memories are a fast form of memory implemented widely in modern day processors to bridge the memory wall between the CPU and the main memory. We address the timing channels leakages possible on cryptographic implementations due to the presence of cache memories. We also address the effect of the presence in several contemporary architectural artefacts, which includes out of order execution, hardware prefetchers, etc. Finally, we conclude the talk with a discussion on an ideal quest for cipher implementations and show that if studied well the influence of micro-architecture on leakage can be capitalized to develop robust implementations.