First Workshop on

MicroArchitectural Security

October 11th-12th,
Indian Institute of Technology, Madras




Workshop

Over the last four decades, microprocessor research has focussed on improving performance. Various micro architectural features such as cache memories, branch prediction, superscalar, speculative and out-of-order execution, were developed to facilitate this. Side-by-side, features such as multiprogramming, multicore and hardware multithreading were incorporated to increase throughput. These features allowed multiple users to simultaneously share a processor. To isolate one user’s program from another, rudimentary security schemes such as protection rings and page table access controls bits were used. Very soon it was realized that these security schemes were insufficient. Vulnerabilities in software permitted user space programs to gain privileged access. Shared hardware became a source of information leaks that could undermine the isolation provided. The very features in the processor that were incorporated to boost performance and throughput have now become a security liability.

The last few months have seen an exodus of attacks like Meltdown and Spectre, SPOILER, Zombieload, and SWAPGS. Each attack finds a new vulnerability that can bypass the isolation installed. Most of these attacks are not easily prevented. Every software patch developed has huge performance penalties. These recent developments have led to several questions and open challenges.

Where did we go wrong with processor design? Are there any more of such attacks yet to come? How do we build efficient countermeasures? How should processors be designed that can prevent all attacks, present and future? How do we verify and validate processors for security? Where do we tradeoff between performance and security?

This workshop, a part of Shakti Week, will gather experts from industry and academia to discuss and ponder about these questions. The workshop would have two full days of invited talks, panel discussions, and poster sessions, focussed on security with the hope of laying the foundations for safe and secure future microprocessors.




Topics of Interest




Speakers

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Avi (Abraham) Mendelson

Title of the talk: Securing modern high-performance processors - challenges and possible solutions.

Avi Mendelson has a blend of industrial and academic experience in several different areas such as computer architecture, operating systems, power management, reliability, and high-performance computing. He received a PhD in computer engineering from the University of Massachusetts at Amherst in 1990. Among his industrial jobs, he served as the manager of the academic outreach program at Microsoft R&D Israel, where he initiated different innovation-based activities among students. Before that, he worked for 11 years as a senior researcher and principle engineer at Intel. Among his achievements at Intel, he was the chief architect of the CMP (multicore-on-chip) feature of the first dual-core processors Intel developed. For this work, he received the Intel Achievement Award (the highest award at Intel). Mendelson has published more than 130 papers in refereed journals, conferences, and workshops. He completed a full term as an associate editor of IEEE Computer Architecture Letters (CAL) a nd now serves as an associate editor of IEEE Transactions on Computers . He served as program chair of different major conferences and as the general chair of the ISCA (International Symposium on Computer Architecture) in 2013.

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Debdeep Mukhopadhyay

Title of the talk: Micro-architectural Attacks: Where Architecture meets Cryptography (abstract)

Dr. Debdeep Mukhopadhyay is currently an Professor at the Department of Computer Science and Engineering, Indian Institute of Technology at Kharagpur, India and a visiting scientist at School of Computer Science and Engineering at NTU, Singapore. At IIT Kharagpur he initiated the Secured Embedded Architecture Laboratory (SEAL), with a focus on Embedded Security and Side Channel Attacks. Prior to this he worked as a visiting Associate Professor of NYU-Shanghai. He had also served as an Assistant Professor at IIT Madras, India and as a Visiting Researcher at NYU Polytechnic School of Engineering under the Indo-US STF Fellowship. He holds a PhD, an MS, and a B. Tech from IIT Kharagpur, India. Dr. Mukhopadhyay’s research interests are Cryptography, Hardware Security, and VLSI. His books include Cryptography and Network Security (Mc GrawHills), Hardware Security: Design, Threats, and Safeguards (CRC Press), and Timing Channels in Cryptography (Springer). He has written more than 100 papers in peer-reviewed conferences and journals and has collaborated with several Indian and Foreign Organizations. Dr. Mukhopadhyay is the recipient of the prestigious Swarnajayanti DST Fellowship 2015-16, Young Scientist award from the Indian National Science Academy, the Young Engineer award from the Indian National Academy of Engineers, and is a Young Associate of the Indian Academy of Science. He was also awarded the Outstanding Young Faculty fellowship in 2011 from IIT Kharagpur, and the Techno-Inventor Best PhD award by the Indian Semiconductor Association. He has recently incubated a start-up on Hardware Security, ESP Pvt Ltd at IIT Kharagpur.

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Biswabandan Panda

Title of the talk: Hardware Prefetchers and Security: A Two-Edged Sword (abstract)

Biswa is an Assistant Professor at the CSE dept. of IIT Kanpur. Prior to that, he was at the PACAP team of INRIA, Rennes, working with André Seznec. He received his Ph.D. and Masters from Indian Institute of Technology Madras. His area of research includes performance and security issues related to memory systems.

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Vinay B. Kumar

Title of the talk: Building blocks of a secure system-on-chip (abstract)

Vinay is a Postdoctoral Research Fellow at the School of Computer Science and Engineering in Nanyang Technological University (Singapore) since January 2019, where he is part of the SOCure project, a research programme towards secure SoC design. His other interests include high-level synthesis, NoC-based design and high-performance computing. He received his Ph.D. and B.Tech+M.Tech degrees from IIT Bombay in 2019 and 2008 respectively. Prior to Ph.D., he was at ASUS, Taipei, for three years.

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Sarani Bhattacharya

Title of the talk: Micro-architectural Attacks and defences on Branch Prediction (abstract)

Sarani Bhattacharya is currently a post-doctoral research student at the COSIC, Electrical Engineering Department of KU Leuven, Belgium. She has received her PhD degree in Computer Science and Engineering from Indian Institute of Technology Kharagpur. Her Ph.D research is titled as "Micro-Architectural Attacks and Countermeasures on Public-key Cryptosystems" and she works on the vulnerability analysis of micro-architectural components with an emphasis on branch predictors.

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Mohan Parthasarathy

Title of the talk: Meltdown and Spectre: From the Attacks to its Defenses (abstract)

Mohan Parthasarathy is a Lead Technical Architect in the Compute Solutions Business Unit of Hewlett Packard Enterprise (HPE). He is the system architect for the Superdome2 and Superdome X platforms, and is based in Bangalore, India. His primary focus currently is on Operating System and Platform/Firmware aspects of scale-up Integrity and x86 servers. He has over 20 years of industry experience, and has worked on multiple areas of operating systems, including networking protocol stacks, drivers, core kernel and virtualization. Mohan did his Masters in Electrical Engineering from the Indian Institute of Science, Bangalore, and is a co-inventor of 5 US patents.

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Joydeep Rakshit

Title of the talk: Efficient security for memory: A hardware perspective (abstract)

Joydeep Rakshit is a Research Scientist in the Processor Architecture Research Lab (PARL) at Intel Labs, Bangalore. Currently, he is working on efficient memory hierarchies to loosen the memory bottleneck. He completed his Ph.D. from University of Pittsburgh in 2018 where he worked on architecting efficient solutions to ensure confidentiality and integrity of data in main memory. Joydeep received the A. Richard Newton Young Fellow Award at the Design Automation Conference (DAC) 2016. He has served as reviewer for DAC, TVLSI, and ACM Computing Surveys.

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Arjun Menon

Title of the talk:Securing the Shakti Processor (abstract)

Arjun Menon is a Senior Project Officer in the Department of Computer Science and Engineering at IIT Madras. His areas of interest include microprocessor design, high-performance computing, and hardware security. He is one of the architects behind India’s first indigenously developed RISC-V processor (Shakti) and has been involved in the project ever since it's inception. He has obtained his Master’s degree in Computer Science and Engineering from IIT Madras, and his bachelor’s degree in Electronics and Communication Engineering from Amrita School of Engineering.




Program

Day 1 : 11th October 2019

9:30 -- 10:00

Inauguration

10:00 -- 10:45
Micro-architectural Attacks: Where Architecture meets Cryptography
Debdeep Mukhopadhyay, IIT Kharagpur
10:45 -- 11:15

Tea Break

11:15 -- 12:00
Hardware Prefetchers and Security: A Two-Edged Sword
Biswabandan Panda, IIT Kanpur
12:00 -- 12:45
DRAM and NVRAM Security
Joydeep Rakshit, Intel
12:45 -- 14:00

Lunch / Poster session

14:00 -- 14:45
Micro-architectural Attacks and defences on Branch Prediction
Sarani Bhattacharya, KU Leuven, Belgium
14:45 -- 15:30
Building blocks of a secure system-on-chip
Vinay Kumar, NTU, Singapore
15:30 -- 16:00

Tea Break

16:00 -- 16:45
Meltdown and Spectre: From the Attacks to its Defenses
Mohan Parthasarathy, Hewlett Packard Enterprise.


Day 2 : 12th October 2019

10:00 -- 10:45
Securing modern high-performance processors -- challenges and possible solutions
Avi Mendelson, Technion, Israel
10:45 -- 11:15

Tea Break

11:15 -- 12:00
Securing the Shakti Processor
Arjun Menon, IIT Madras
12:00 -- 13:15
Security in Microprocessors: The Road Ahead
Panel Discussion
13:15 -- 15:30

Lunch Break / Poster Session