- In-order 3 stage 32/64 bit microcontroller supporting a subset of RISC-V ISA.
- Low area and power consumption - operational frequency of less than 200MHz on silicon.
- Optimized variants for FPGA based soft-cores.
- AXI4/AXI4-Lite/TileLink peripherals supported.
- Positioned against ARM's M class cores.
- Open source IP supporting RV32/64 - IMAC.
- Optional Direct-mapped caches for instruction and data.
- Supports Machine and User-modes only.
- User-mode trap handling is optional.
- Push button flow to generate variants and subsets of ISA.
- Optimized sequential Multiplier and Divider for ASICs and FPGAs. 41.30.6:8880/
- OpenOCD based SoC debug support through JTAG.
- OS Ports: FreeRTOS, Zephyr.
This implementation has also been burnt on FPGA's and it consumes less than 3K LUT's on a 7-series Xilinx FPGA.