- An in-order 6-stage 64-bit microcontroller supporting the entire stable RISC-V ISA.
- Targets mid-range compute systems: 200-800MHz (can be customized for 2 Ghz applications)
- Supports RISC-V Linux, secure L4
- Variants for low-power and high-performance.
- Positioned against ARM’s Cortex A35/A55.
- Supports RISC-V ISA: RV64IMAFD.
- Compatible with latest privilege spec (v1.10) of RISC-V ISA and supports the sv39/48 virtualization scheme.
- Single and Double Precision Floating point units compliant with IEEE-754.
- Supports the OpenOCD based debug environment through JTAG.
- Includes a High performance branch predictor with a Return-Address-Stack.
- Caches: 16-64KB non-blocking pipelined Instruction and Data caches. Optional L2.
- Includes operand forwarding scheme for better performance.
- Boots RISC-V Linux.
We have successfully taped out a 22nm chip using this design which boots RISC-V Linux. It consumes 90-110 mW power on 22nm and requires about 175k gates for realization. The same core has also been manufactured as a Test-chip on the 180nm from SCL. Find more details HERE.
This implementation has also been targeted on FPGA's and it consumes about 20K LUT's on a 7-series Xilinx FPGA and reports DMIPS/MHz of 1.68